1. Field of the Invention
The present invention relates to a push-pull amplifier which operates with low consumption current at no load, and has a high current driving capacity.
2. Description of the Related Art
Up to now, push-pull amplifiers having a great variety of configurations have been proposed, and they find their proper applications, based on the respective purposes, and the requirements for power supply voltage, and the like.
Among them, as the push-pull amplifier which operates at low voltage, the circuit as shown in FIG. 4 is known (referring to Japanese Patent Laid-Open No. 2005-311865). As shown in FIG. 4, this push-pull amplifier includes a differential amplifier circuit 1, a differential difference amplifier circuit 17, a level shifting circuit 3, and an output amplifier circuit 4. Further, this push-pull amplifier includes an inversion input terminal 5, a non-inversion input terminal 6, and an output terminal 16.
Generally, the push-pull amplifier is configured as an operational amplifier, including a differential amplifier circuit 1, however, it may lack the differential amplifier circuit 1, or include some other type of amplifier circuit. In this example of related art, the push-pull amplifier which is often used in general, including the differential amplifier circuit 1, will be described.
The differential amplifier circuit 1, which has the inversion input terminal 5 and the non-inversion input terminal 6, is a circuit which carries out differential amplification of an input signal fed to these both input terminals 5, 6. The output terminal 10 of this differential amplifier circuit 1 is connected to a first inversion input terminal of the differential difference amplifier circuit 17, and to the gate of an MOS transistor M24 in the output amplifier circuit 4.
The differential difference amplifier circuit 17 is a circuit which receives an output signal from the differential amplifier circuit 1 at the first inversion input terminal; inverts this received signal; and feeds the inverted signal to the gate of an MOS transistor M22 in the level shifting circuit 3 as an output signal.
Thus, the differential difference amplifier circuit 17 includes, besides the above-mentioned first inversion input terminal, a second inversion input terminal, a first non-inversion input terminal, a second non-inversion input terminal, and an output terminal 14, and the second inversion input terminal is connected to the output terminal 14. Further, the two non-inversion input terminals are connected to a reference voltage terminal 12, and to the respective non-inversion input terminals, a reference voltage Vref1 is supplied.
The level shifting circuit 3 is a circuit which carries out level shift of the output signal from the differential difference amplifier circuit 17, while inverting the output signal, and combines a P-type MOS transistor M21 with an N-type MOS transistor M22.
In other words, a power supply voltage VDD is supplied to the source of the MOS transistor M21, the gate and drain of which are commonly connected. And, the common connection is connected to the gate of the MOS transistor M23 in the output amplification section 4, and the drain of the MOS transistor M22, respectively. An output signal of the differential difference amplifier circuit 17 is fed to the gate of the MOS transistor M22, and to the source thereof, a power supply voltage VSS is supplied.
The output amplifier circuit 4 includes complementary MOS transistors M23, M24 which are different from each other in polarity, and the MOS transistors M23, M24 provide a circuit being inputted with an output signal of the level shifting circuit 3 and an output signal of the differential amplifier circuit 1 to make push-pull amplification operation.
In other words, the power supply voltage VDD is supplied to the source of the P-type MOS transistor M23, and the gate thereof is connected to an output terminal 15 of the level shifting circuit 3. The drain of the MOS transistor 23 is connected to the drain of the N-type MOS transistor M24, and the common connection therebetween is connected to the output terminal 16. Further, an output signal of the differential amplifier circuit 1 is fed to the gate of the MOS transistor M24, and to the source thereof, the power supply voltage VSS is supplied.
Next, an example of configuration of a circuit which is applicable to the differential difference amplifier circuit 17 will be described with reference to FIG. 5.
As shown in FIG. 5, the differential difference amplifier circuit includes a differential input section 31 including N-type MOS transistors M1, M2, M5; a differential input section 32 including N-type MOS transistors M3, M4, M6; and an adder section 33 including P-type MOS transistors M7 to M10 and N-type MOS transistors M11, M12 which adds the output of the differential input section 31 to the output of the differential input section 32. Herein, the MOS transistors M7, M8 are used as common loads for the differential input section 31 and the differential input section 32.
In addition, as shown in FIG. 5, this differential difference amplifier circuit includes a first non-inversion input terminal 34, a first inversion input terminal 35, a second inversion input terminal 36, a second non-inversion input terminal 37, and an output terminal 38.
More particularly, the MOS transistors M1, M2 form a differential pair, the gate of the MOS transistor M1 being connected to the first non-inversion input terminal 34, and the gate of the MOS transistor M2 being connected to the first inversion input terminal 35. The MOS transistors M3, M4 form a differential pair, the gate of the MOS transistor M3 being connected to the second inversion input terminal 36, and the gate of the MOS transistor M4 being connected to the second non-inversion input terminal 37.
The MOS transistor M5 functions as a constant current source for the MOS transistors M1, M2, and the MOS transistor M6 functions as a constant current source for the MOS transistors M3, M4. To that end, the respective gates of the MOS transistors M5, M6 are connected to a bias terminal 39, and to those respective gates, a prescribed bias voltage is supplied.
The respective gates of the MOS transistors M7, M8 are connected to a bias terminal 40, and to those respective gates, a prescribed bias voltage is supplied. In addition, the respective gates of the MOS transistors M9, M10 are connected to a bias terminal 41, and to those respective gates, a prescribed bias voltage is supplied. Further, the MOS transistor M11, M12 constitute a current mirror circuit.
Next, as shown in FIG. 5, the operation of the differential difference amplifier circuit will be described.
Now, let's assume that, as shown in FIG. 5, in the differential difference amplifier circuit, an input voltage V1, V2 is supplied to the input terminal 34, 35, while an input voltage V4, V3 is supplied to the input terminal 36, 37, respectively. In addition, assuming that the output voltage of the output terminal 38 is VOUT, the relationship among these voltages can be expressed by the following equation:VOUT=A1(V1−V2)+A2(V3−V4)  (1)where A1 in Eq. (1) is the gain from the input terminal 34, 35 to the output terminal 38, and A2 is the gain from the input terminal 36, 37 to the output terminal 38.
Now, let's assume that the respective sizes of the MOS transistors M1 to M4 are the same, and the respective sizes of the MOS transistors M5, M6 are the same, then the gains A1, A2 will be equal to each other, thus A1=A2=A becomes true, which allows Eq. (1) to be rearranged into the following Eq. (2):VOUT=A(V1−V2+V3−V4)  (2)
Herein, if the gain for the differential difference amplifier circuit is large enough, V1−V2+V3−V4=0 becomes true from Eq. (2), provided the differential difference amplifier circuit is used in a feedback circuit. If this relationship is applied to the output signal of the differential difference amplifier circuit 17 in FIG. 4, the relationship expressed by the following Eq. (3) is obtained.V14=2×Vref1−V10  (3)where V10 is the voltage at the output terminal 10 of the differential amplifier circuit 1, and V14 is the voltage at the output terminal 14 of the differential difference amplifier circuit 17.
From Eq. (3), it can be seen that the output voltage V14 for the differential difference amplifier circuit 17 is an inversion of the input voltage for the differential difference amplifier circuit 17. In addition, the voltage V15 at the output terminal 15 in the level shifting circuit 3 is an inversion of the voltage V14 at the output terminal 14 in the differential difference amplifier circuit 17.
Now, assuming that the voltage V10 at the output terminal 10 of the differential amplifier circuit 1 is a sine wave voltage, then the relationship among the respective waveforms for the voltages V10, V14, V15 at the terminals 10, 14, 15 is as shown in FIG. 6.
In FIG. 6, reference sign D denotes a waveform for the voltage V10 at the output terminal 10 of the differential amplifier circuit 1. The waveform E represents the voltage at the terminal 14, and as can be seen from Eq. (3), it provides an inversion signal as a result of the voltage V10 being inverted. In other words, it can be said that the differential difference amplifier circuit 17 is inputted with the signal D, and inverts it to generate the signal E.
Herein, the signal E at the output terminal 14 of the differential difference amplifier circuit 17 is shifted from the reference level Vref1 to the reference level Vref2 by the level shifting circuit 3, while further being inverted to become a signal F. The polarity of the signal F is the same as the polarity of the signal D as a result of the reinversion.
As a result of such an action of the level shifting circuit 3, in the case where current is to be supplied from the output terminal 16 to the side of the low power supply voltage VSS, the signal level at the terminal 10 is shifted to a level higher than the reference level Vref1. This corresponds to a situation in the vicinity of an arrow 50 in FIG. 6.
Then, the gate voltage for the MOS transistor M24 is increased, which allows more current to be conducted, and on the other hand, the gate voltage for the MOS transistor M23 is increased, which acts so as to reduce the current flow therethrough, resulting in the current conduction in the MOS transistor M24 being promoted.
Conversely, in the case where current is to be supplied from the side of the high power supply voltage VDD to the output terminal 16, the signal level at the terminal 10 is shifted to a level lower than the reference level Vref1. This corresponds to a situation in the vicinity of an arrow 51 in FIG. 6.
Then, the gate voltage for the MOS transistor M24 is decreased, and thus more current can be supplied to the output terminal 16 by the quantity of current flow that has been reduced, and on the other hand, the gate voltage for the MOS transistor M23 is decreased, which allows more current to be conducted.
In this way, the push-pull amplifier circuit acts such that, when one of the output transistors M23, M24 conducts much current, the other transistor acts so as to suppress the quantity of current conducted, or shut off the current. On such a principle, in the case where there is the need for flowing much current, the push-pull amplifier circuit can make the desired operation while suppressing the consumption current.
In order to allow the output MOS transistor M23, M24 to drive a higher output current, the level of the signal to be applied to the gate of the MOS transistor M23, M24 can be increased. For example, for the MOS transistor M24, the peak level of the signal waveform D in FIG. 6 can be increased.
However, if the peak level of the signal waveform D is increased with respect to Vref1, the difference in voltage from the signal waveform E at a peak is increased. In this case, if a signal which level is high enough to turn off any of the input transistors M1 to M4 in the differential difference amplifier 17 is applied, the differential difference amplifier circuit 17 will not perform the computation as explained with Eq. (2), thus the signal waveform D will not reach a higher level. In order to solve this problem, the overdrive voltage (Vgs−Vth) for the MOS transistors M1 to M4 can be increased, however, the possible range of such increase has been limited.
Therefore, the present invention has been made in consideration of the above-mentioned situation, and the purpose thereof is to provide a push-pull amplifier which, without depending on the overdrive voltage, can increase the peak value of the gate voltage for the output transistor to a level still higher than the conventional one, and is capable of producing an output current with low consumption current that is higher than that available with conventional push-pull amplifiers.